Commit 5b051964 authored by Daniel Scheffler's avatar Daniel Scheffler
Browse files

cleaned up test_COREG.py

parent 68b88f15
Pipeline #416 passed with stages
in 10 minutes and 44 seconds
......@@ -86,7 +86,7 @@ class CompleteWorkflow_INTER1_S2A_S2A(unittest.TestCase):
footprint_poly_tgt=None))
self.assertTrue(CR.success)
#@unittest.skip
def test_shift_calculation_verboseMode(self):
"""Test the verbose mode - runs the functions of the plotting submodule."""
......@@ -164,7 +164,7 @@ class CompleteWorkflow_INTER1_S2A_S2A(unittest.TestCase):
self.skipTest('Not yet implemented.')
#@unittest.skip
def test_plotting_after_shift_calculation(self):
""""""
......
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